The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Dec. 07, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Qiuxia Xu, Beijing, CN;

Huilong Zhu, Poughkeepsie, NY (US);

Tianchun Ye, Beijing, CN;

Huajie Zhou, Beijing, CN;

Gaobo Xu, Beijing, CN;

Qingqing Liang, Lagrangeville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02192 (2013.01); H01L 21/02194 (2013.01); H01L 21/265 (2013.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 29/42364 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01);
Abstract

Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.


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