The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Sep. 02, 2014
Applicant:
Tokyo Electron Limited, Tokyo, JP;
Inventors:
Assignee:
TOKYO ELECTRON LIMITED, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/82 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 25/065 (2006.01); H01L 21/66 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); H01L 21/3065 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 25/0657 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06568 (2013.01);
Abstract
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes forming a mask pattern on a surface of the wafer, and separating each of the semiconductor devices or semiconductor integrated circuits along the mask pattern formed on the surface of the wafer. The mask pattern is a repeated pattern without having a lattice line shape, and the step of separating each of the semiconductor devices or semiconductor integrated circuits is performed by plasma etching.