The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Sep. 01, 2011
Applicant:
Daniel Chu, Folsom, CA (US);
Inventor:
Daniel Chu, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H03K 19/00 (2006.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 7/109 (2013.01); G11C 7/20 (2013.01); H03K 19/00 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06562 (2013.01);
Abstract
A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad.