The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Mar. 15, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ragavendra Natarajan, Mysore, IN;

Jayesh Guar, Bangalore, IN;

Nithiyanandan Bashyam, Bangalore, IN;

Mainak Chaudhuri, Bangalore, IN;

Sreenivas Subramoney, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/08 (2006.01); G06F 13/14 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/0804 (2013.01); G06F 12/0842 (2013.01); G06F 12/126 (2013.01); G06F 12/128 (2013.01); G06F 13/14 (2013.01); G06F 12/084 (2013.01); G06F 2212/62 (2013.01); G06F 2212/69 (2013.01);
Abstract

A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.


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