The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Mar. 12, 2014
Applicants:

Wang Lung Tse, Hong Kong, HK;

Chun Shing Wong, Kwai Chung, HK;

Ka Wing Yeung, Kwai Chung, HK;

Cho Wai Leung, Kwai Chung, HK;

Inventors:

Wang Lung Tse, Hong Kong, HK;

Chun Shing Wong, Kwai Chung, HK;

Ka Wing Yeung, Kwai Chung, HK;

Cho Wai Leung, Kwai Chung, HK;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B65G 11/02 (2006.01); B65G 11/20 (2006.01); H05K 13/00 (2006.01); H05K 13/02 (2006.01);
U.S. Cl.
CPC ...
B65G 11/023 (2013.01); B65G 11/203 (2013.01); H05K 13/0015 (2013.01); H05K 13/027 (2013.01);
Abstract

An apparatus for handling electronic components on a lead frame. The apparatus including a singulation device configured to singulate the lead frame to thereby separate the electronic components and to position the separated electronic components alternately into at least two layers along different levels; and a guide having a plurality of lanes running along a surface of the guide, the lanes being configured to transport the separated electronic components from a first end of the guide arranged adjacent to the singulation device to a second end of the guide arranged adjacent to an output area. The lanes at the first end of the guide are alternately arranged into at least two layers having respective levels to receive the electronic components from the singulation device, whereas the lanes at the second end of the guide are arranged into a single layer along a common level for transferring the electronic components to the output area.


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