The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Dec. 22, 2013
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Daniel Calafut, San Jose, CA (US);

Madhur Bobde, Santa Clara, CA (US);

Yeeheng Lee, San Jose, CA (US);

Hong Chang, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method for forming a dual oxide thickness trench gate structure for a power MOSFET includes providing a semiconductor substrate; forming a first trench on a top surface of the substrate; forming a first oxide layer in the first trench where the first oxide layer has a first depth from the bottom of the first trench; forming a dielectric spacer along the sidewall of the first trench and on the first oxide layer; etching the first oxide layer exposed by the dielectric spacer to a second depth from the bottom of the first trench using the dielectric spacer as a mask where the second depth is lower than the first depth; removing the dielectric spacer; and forming a second oxide layer along the sidewall of the first trench above the first oxide layer where the second oxide layer has a thickness thinner than the thickness of the first oxide layer.


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