The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Aug. 22, 2012
Applicants:

Zhiwei (Tony) Gong, Chandler, AZ (US);

Michael B Vincent, Chandler, AZ (US);

Scott M Hayes, Chandler, AZ (US);

Jason R Wright, Chandler, AZ (US);

Inventors:

Zhiwei (Tony) Gong, Chandler, AZ (US);

Michael B Vincent, Chandler, AZ (US);

Scott M Hayes, Chandler, AZ (US);

Jason R Wright, Chandler, AZ (US);

Assignee:

FREESCALE SEMICONDUCTOR INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/065 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/97 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.


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