The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

May. 29, 2015
Applicant:

Amkor Technology, Inc., Tempe, AZ (US);

Inventors:

Jong Sik Paek, Incheon, KR;

Doo Hyun Park, Gyeonggi-do, KR;

Won Chul Do, Gyeonggi-do, KR;

Pil Je Sung, Seoul, KR;

Jin Hee Park, Seoul, KR;

Do Hyung Kim, Seoul, KR;

In Bae Park, Seoul, KR;

Chang Min Lee, Busan, KR;

Yong Song, Seoul, KR;

Sung Geun Kang, Gyeonggi-do, KR;

Assignee:

Amkor Technology, Inc., Tempe, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 21/563 (2013.01); H01L 24/11 (2013.01); H01L 24/81 (2013.01); H01L 2224/02317 (2013.01);
Abstract

A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.


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