The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2015
Filed:
Dec. 28, 2012
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ilan Pardo, Ramat-Hasharon, IL;
Michael Behar, Zichron Yaakov, IL;
Oren Ben-Kiki, Tel-Aviv, IL;
Dror Markovich, Tel Aviv, IL;
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/08 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); Y02B 60/1225 (2013.01);
Abstract
A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.
Pardo, Ilan. (2015). Apparatus and method for memory-mapped register caching (U.S. Patent No. 9189398). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9189398
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