The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Dec. 27, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jiyoung Kim, Yongin-si, KR;

Daeik Kim, Hwaseong-si, KR;

Kang-Uk Kim, Seoul, KR;

Nara Kim, Seongnam-si, KR;

Jemin Park, Suwon-si, KR;

Kyuhyun Lee, Hwaseong-si, KR;

Hyun-Woo Chung, Yongin-si, KR;

Gyoyoung Jin, Seoul, KR;

HyeongSun Hong, Seongnam-si, KR;

Yoosang Hwang, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/48 (2006.01); H01L 21/683 (2006.01); H01L 27/06 (2006.01); H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/6835 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/0688 (2013.01); H01L 27/1464 (2013.01); H01L 27/14632 (2013.01); H01L 27/14634 (2013.01); H01L 27/10897 (2013.01); H01L 2221/6835 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68363 (2013.01); H01L 2223/54426 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.


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