The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2015
Filed:
Dec. 14, 2012
Intel Corporation, Santa Clara, CA (US);
Ren Wang, Portland, OR (US);
Ahmad Samih, Beaverton, OR (US);
Eric Delano, Fort Collins, CO (US);
Pinkesh J. Shah, Chandler, AZ (US);
Zeshan A. Chishti, Hillsboro, OR (US);
Christian Maciocco, Portland, OR (US);
Tsung-Yuan Charlie Tai, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.