The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Feb. 28, 2014
Applicants:

Stefano Giaconi, Phoenix, AZ (US);

Mingming Xu, Phoenix, AZ (US);

Inventors:

Stefano Giaconi, Phoenix, AZ (US);

Mingming Xu, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/081 (2006.01); H04L 7/033 (2006.01); H03M 1/74 (2006.01); H03M 1/66 (2006.01); H03M 1/10 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01); H03M 7/30 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0814 (2013.01); H04L 7/0332 (2013.01); H03K 5/135 (2013.01); H03K 2005/00058 (2013.01); H03M 1/1023 (2013.01); H03M 1/66 (2013.01); H03M 1/742 (2013.01); H03M 1/745 (2013.01); H03M 7/3006 (2013.01);
Abstract

Described is an apparatus which comprises: a current steering digital-to-analog converter (DAC) to receive a digital bus to control current steering; a switch capacitor network to integrate currents from the DAC, the switch capacitor network having switches which are controllable by a plurality of digital clock signals; an output stage to compare the integrated currents against at least two threshold voltages and to generate an output signal; and a duty cycle corrector (DCC) operable to adjust the at least two threshold voltages to modify duty cycle of the output signal.


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