Mos transistor, fabrication method thereof, and sram memory cell circuit

Abstract

Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased.