The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Dec. 08, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Dong Hyuk Kim, Seongnam-si, KR;

Hoi Sung Chung, Hwaseong-si, KR;

Myungsun Kim, Hwaseong-si, KR;

Dongsuk Shin, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7834 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 29/0692 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.


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