The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Jan. 29, 2015
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Seung-Chul Song, San Diego, CA (US);
James W. Blatchford, Richardson, TX (US);
Kwan-Yong Lim, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6659 (2013.01); H01L 21/265 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66628 (2013.01); H01L 29/7834 (2013.01);
Abstract
A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.