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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9177858 B1

PDFFull Text
Date of Patent:
Nov. 03, 2015

Filed:

May. 08, 2014

Methods for fabricating integrated circuits including barrier layers for interconnect structures

Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

Xunyuan Zhang, Albany, NY (US);

Tibor Bolom, Litomerice, CZ;

Kun Ho Ahn, Dresden, DE;

Bernd Hintze, Langebrueck, DE;

Frank Koschinsky, Radebeul, DE;

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:

Ingrassia Fisher & Lorenz, P.C.

Primary Examiner:

Tu-Tu Ho

Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7685 (2013.01); H01L 21/2855 (2013.01); H01L 21/28556 (2013.01); H01L 21/28568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76834 (2013.01); H01L 21/76843 (2013.01); H01L 21/76871 (2013.01); H01L 21/76879 (2013.01);
Abstract

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Find Patent Forward Citations

Zhang, Xunyuan. (2015). Methods for fabricating integrated circuits including barrier layers for interconnect structures (U.S. Patent No. 9177858). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9177858

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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