The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Mar. 16, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Xavier Vera, Barcelona, ES;
Javier Carretero Casado, Barcelona, ES;
Enric Herrero Abellanas, Cardedeu, ES;
Daniel Sanchez, L'Hospitalet de Llobregat, ES;
Nicholas Axelos, Barcelona, ES;
Tanausu Ramirez, Barcelona, ES;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2006.01); G06F 12/08 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/126 (2013.01); G06F 11/00 (2013.01); G06F 12/0895 (2013.01); Y02B 60/1225 (2013.01);
Abstract
A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.