The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Dec. 18, 2013
Applicant:

Shenzhen Goldsun Network Intelligence Technology Co., Ltd., ShenZhen, CN;

Inventors:

Shao-You Tang, New Taipei, TW;

Po-Chuan Hsieh, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0225 (2013.01); H05K 1/0222 (2013.01); H05K 1/0245 (2013.01); H05K 1/0253 (2013.01); H05K 1/16 (2013.01); H05K 2201/09254 (2013.01); H05K 2201/09618 (2013.01); H05K 2201/09627 (2013.01);
Abstract

A printed circuit board (PCB) includes a ground layer, a first layer, a second layer, a connector footprint, and a pair of differential signal lines. The connector footprint comprises first and second bonding pads. The PCB defines a first signal via in a central portion of a space bounded by the first bonding pad, and a second signal via in a central portion of a space bounded by the second bonding pad. A number of first ground vias on the first bonding pad and a number of second ground vias on the second bonding pad are electrically connected to the ground layer. First annular slots surrounding corresponding first ground via are defined in the ground layer. Second annular slots surrounding corresponding second ground vias are defined in the ground layer. Connection slots are defined in the ground layer and communicate between the first annular slots and the second annular slots.


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