The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

May. 15, 2014
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventor:

Tzu-Ping Chen, Hsinchu County, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region.


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