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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9171797 B1

PDFFull Text
Date of Patent:
Oct. 27, 2015

Filed:

Jun. 05, 2013

System-in-package having integrated passive devices and method therefor

Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Yaojian Lin, Singapore, SG;

Robert C. Frye, Piscataway, NJ (US);

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:

Robert D. Atkins

Patent Law Group Atkins and Associates, P.C.

Primary Examiner:

Luan C Thai

Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01); H01L 25/16 (2006.01); H05K 1/16 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H05K 3/20 (2006.01); H05K 3/28 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 23/52 (2013.01); H01L 21/56 (2013.01); H01L 21/6835 (2013.01); H01L 23/5383 (2013.01); H01L 23/64 (2013.01); H01L 25/16 (2013.01); H05K 1/16 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83005 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/1532 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/30107 (2013.01); H05K 3/20 (2013.01); H05K 3/284 (2013.01); H05K 3/4644 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49146 (2015.01); Y10T 29/49155 (2015.01); Y10T 29/49165 (2015.01);
Abstract

A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

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