The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Nov. 27, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Andrew T. Forsyth, Kirkland, WA (US);

Ramacharan Sundararaman, Hillsboro, OR (US);

Eric Sprangle, Austin, TX (US);

John C. Mejia, Hillsboro, OR (US);

Douglas M. Carmean, Hillsboro, OR (US);

Edward T. Grochowski, San Jose, CA (US);

Robert D. Cavin, San Francisco, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/126 (2013.01); G06F 12/123 (2013.01); Y02B 60/1225 (2013.01);
Abstract

In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.


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