The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2015
Filed:
Dec. 21, 2012
Herbert H. Hum, Portland, OR (US);
James R. Vash, Littleton, MA (US);
Eric A. Gouldey, Fort Collins, CO (US);
Ganesh Kumar, Fort Collins, CO (US);
David Bubien, Fort Collins, CO (US);
Manoj K. Arora, Bangalore, IN;
Luke Chang, Aloha, OR (US);
Lavanya Nama, Warangal, IN;
Mahak Gupta, Bangalore, IN;
Herbert H. Hum, Portland, OR (US);
James R. Vash, Littleton, MA (US);
Eric A. Gouldey, Fort Collins, CO (US);
Ganesh Kumar, Fort Collins, CO (US);
David Bubien, Fort Collins, CO (US);
Manoj K. Arora, Bangalore, IN;
Luke Chang, Aloha, OR (US);
Lavanya Nama, Warangal, IN;
Mahak Gupta, Bangalore, IN;
Intel Corporation, Santa Clara, CA (US);
Abstract
Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.