The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
Jun. 30, 2014
Applicant:
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Inventors:
Francis Poh, Singapore, SG;
Shifeng Zhao, Singapore, SG;
Yang Hong, Ottobrunn, DE;
Tze Ho Simon Chan, Singapore, SG;
Assignee:
GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/02 (2006.01); G11C 13/00 (2006.01); G11C 5/06 (2006.01); G11C 11/40 (2006.01); G11C 8/00 (2006.01); G11C 5/02 (2006.01); G11C 8/14 (2006.01); H01L 27/24 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 13/0002 (2013.01); H01L 27/2436 (2013.01); G11C 5/025 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 13/003 (2013.01); G11C 2213/74 (2013.01);
Abstract
Disclosed herein are memory cell arrays, semiconductor devices, and methods for fabricating semiconductor devices. In one embodiment, a memory cell array includes first, second, third, and fourth memory cells each having a first transistor and a second transistor. First and second word-lines are coupled with the gates of the first transistors of the first and second memory cells. The second and a third word-line are coupled with the gates of the second transistors of the third and fourth memory cells.