The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Mar. 10, 2008
Applicant:

George Dudnikov, San Jose, CA (US);

Inventor:

George Dudnikov, San Jose, CA (US);

Assignee:

Sanmina-SCI Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H01G 4/06 (2006.01); H01G 4/30 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/162 (2013.01); H01G 4/06 (2013.01); H01G 4/30 (2013.01); H01G 4/306 (2013.01); H05K 1/0216 (2013.01); H05K 1/0231 (2013.01); H05K 1/18 (2013.01); H05K 3/4641 (2013.01); H05K 1/113 (2013.01); H05K 3/4602 (2013.01); H05K 2201/0191 (2013.01); H05K 2201/0209 (2013.01); H05K 2201/0257 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/093 (2013.01); H05K 2201/09309 (2013.01); H05K 2201/09518 (2013.01); H05K 2201/09663 (2013.01); H05K 2203/162 (2013.01); Y10T 29/43 (2015.01); Y10T 29/435 (2015.01); Y10T 29/49036 (2015.01); Y10T 29/49126 (2015.01); Y10T 29/49128 (2015.01); Y10T 29/49155 (2015.01);
Abstract

A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.


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