The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Jun. 20, 2014
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Sang Choon Ko, Daejeon, KR;

Jae Kyoung Mun, Daejeon, KR;

Woojin Chang, Daejeon, KR;

Sung-Bum Bae, Daejeon, KR;

Young Rak Park, Daejeon, KR;

Chi Hoon Jun, Daejeon, KR;

Seok-Hwan Moon, Daejeon, KR;

Woo-Young Jang, Seoul, KR;

Jeong-Jin Kim, Jeonju-si, KR;

Hyungyu Jang, Cheongju-si, KR;

Je Ho Na, Seoul, KR;

Eun Soo Nam, Daejeon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/33 (2006.01); H01L 21/321 (2006.01); H01L 21/02 (2006.01); H01L 21/283 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3212 (2013.01); H01L 21/0254 (2013.01); H01L 21/283 (2013.01);
Abstract

Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.


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