The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Sep. 28, 2012
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Sandeep Brahmadathan, Bangalore, IN;

Srinivas Suresh Revankar, Bangalore, IN;

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/04 (2013.01); G11C 16/0483 (2013.01);
Abstract

The present invention provides a method and system to reduce the impact of errors introduced in flash devices while providing improved system performance through optimized activities with limited impact to overhead using a predetermined threshold value or threshold device value. In an embodiment, a device threshold value is compared with the cumulative number of data bits having a zero value of a target page and an error type of the target page is assessed to determine whether the target page is available to be written to. Therefore for a highly effective method for is provided for determining the availability of a page, having a block address and page address, to be identified, in one instance, as being an erased page that is available to be written to.


Find Patent Forward Citations

Loading…