The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Nov. 21, 2011
Applicants:

Jonathan W. Ward, Fairfax, VA (US);

Adrian N. Robinson, Haymarket, VA (US);

Garo J. Derderian, Manassas, VA (US);

Inventors:

Jonathan W. Ward, Fairfax, VA (US);

Adrian N. Robinson, Haymarket, VA (US);

Garo J. Derderian, Manassas, VA (US);

Assignee:

Lockheed Martin Corporation, Bethesda, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/02 (2006.01);
U.S. Cl.
CPC ...
G11C 13/025 (2013.01); G11C 2213/17 (2013.01); G11C 2213/70 (2013.01); G11C 2213/76 (2013.01);
Abstract

A three-dimensional (3-D) memory stack and a method of formation thereof are described. The 3-D memory stack includes a number of vertically stacked memory devices. Each memory device includes one or more memory cells. Each of the memory cells can be formed on a conductive material. Each memory device further includes one or more selector elements each configured to couple a memory cell of the one or more memory cells to a respective bit line. None of the selector elements is configured as a diode or a transistor element.


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