The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Mar. 30, 2012
Applicants:

Darshan Kobla, Austin, TX (US);

David J. Zimmerman, Folsom, CA (US);

Vimal K. Natarajan, Portland, OR (US);

Inventors:

Darshan Kobla, Austin, TX (US);

David J. Zimmerman, Folsom, CA (US);

Vimal K. Natarajan, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 11/4097 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1016 (2013.01); G11C 11/4097 (2013.01); G11C 29/4401 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/4402 (2013.01);
Abstract

An apparatus, system, and method provide for on chip redundancy repair for stacked memory devices. A memory device may include a memory stack including one or more layers of dynamic random-access memory (DRAM) and a system element coupled with the memory stack, the system element including a memory controller for control of the memory stack, and repair logic that is coupled with the memory controller. The repair logic is to hold repair addresses that are identified as failing addresses for defective areas of the memory stack, with the repair logic to receive a memory operation request and implement redundancy repair for an operation address for the request using a repair logic memory to store the repair addresses and data for the repair addresses.


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