The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Mar. 15, 2013
Applicant:

Genesis Photonics Inc., Tainan, TW;

Inventors:

Cheng-Hung Lin, Tainan, TW;

Yu-Yun Lo, Tainan, TW;

Cheng-Yen Chen, Tainan, TW;

Yu-Hung Lai, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/36 (2010.01); H01L 33/00 (2010.01); H01L 27/15 (2006.01);
U.S. Cl.
CPC ...
H01L 33/36 (2013.01); H01L 27/15 (2013.01); H01L 33/005 (2013.01); H01L 33/0095 (2013.01); H01L 2933/0025 (2013.01);
Abstract

A method of forming light emitting diode dies includes: forming an epitaxial layered structure that defines light emitting units on a front surface of a substrate wafer; forming a photoresist layer over a back surface of the substrate wafer; aligning the substrate wafer and patterning the photoresist layer so as to form openings in the photoresist layer, each of the openings having an area less than a projected area of the respective light emitting unit; forming a solder layer on the photoresist layer such that the solder layer fills the openings in the photoresist layer; removing the photoresist layer and a portion of the solder layer that covers the photoresist layer from the substrate wafer; and dicing the substrate wafer.


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