The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Apr. 04, 2014
Applicant:
Halo Lsi, Inc., Hillsboro, OR (US);
Inventors:
Seiki Ogura, Hillsboro, OR (US);
Tomoko Iwasaki, Hillsboro, OR (US);
Nori Ogura, Hillsboro, OR (US);
Assignee:
Halo LSI, Inc., Hillsboro, OR (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10876 (2013.01); G11C 16/10 (2013.01); H01L 21/28282 (2013.01); H01L 27/108 (2013.01); H01L 27/10879 (2013.01); H01L 27/11563 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 29/66666 (2013.01); H01L 29/66833 (2013.01); H01L 29/7827 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01);
Abstract
A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.