The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
May. 20, 2014
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Se-Aug Jang, Gyeonggi-do, KR;
Hong-Seon Yang, Gyeonggi-do, KR;
Ja-Chun Ku, Gyeonggi-do, KR;
Seung-Ryong Lee, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 27/108 (2006.01); H01L 27/105 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 27/1052 (2013.01); H01L 27/10808 (2013.01); H01L 27/10891 (2013.01); H01L 29/4236 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01);
Abstract
A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer.