The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Jun. 30, 2014
Applicant:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Inventors:

Sunil Kumar Sharma, Fremont, CA (US);

Amit Singh, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5054 (2013.01); G06F 17/505 (2013.01);
Abstract

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The computer-implemented method also includes synthesizing the design into a plurality of PLD components. In the computer-implemented method, the synthesizing includes detecting an incrementer-multiplier operation in the design and merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.


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