The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2015
Filed:
Jan. 15, 2015
AU Optronics Corp., Hsin-Chu, TW;
Yi-Chen Chung, Hsin-Chu, TW;
Chia-Yu Chen, Hsin-Chu, TW;
Hui-Ling Ku, Hsin-Chu, TW;
Yu-Hung Chen, Hsin-Chu, TW;
Chi-Wei Chou, Hsin-Chu, TW;
Fan-Wei Chang, Hsin-Chu, TW;
Hsueh-Hsing Lu, Hsin-Chu, TW;
Hung-Che Ting, Hsin-Chu, TW;
AU Optronics Corp., Hsin-Chu, TW;
Abstract
A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.