The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Nov. 14, 2014
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Cheng-Han Wu, Taichung, TW;

Chun-Chi Yu, Taipei, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/302 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 21/033 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/0276 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01);
Abstract

The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.


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