The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9144157 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 22, 2015

Filed:

Jul. 28, 2011
Applicant:

Hiroto Iida, Saitama, JP;

Inventor:

Hiroto Iida, Saitama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/09 (2006.01); H05K 3/06 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 3/42 (2006.01); H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
H05K 3/06 (2013.01); H05K 1/0298 (2013.01); H05K 3/425 (2013.01); H05K 3/4652 (2013.01); H05K 3/386 (2013.01); H05K 3/421 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/0358 (2013.01); H05K 2201/09563 (2013.01);
Abstract

Object of the present invention is to provide a method for manufacturing a printed wiring board which enables fine wiring formation at low costs and with high yields without introducing any special equipment, and a printed wiring board manufactured by the method. To achieve the object, a method for forming the wiring pattern adopted includes steps; for forming a laminate having a structure in which a copper foil layer formed using copper foil without roughening treatment having surface roughness (Rzjis) at a bonding surface of 2 μm or less and thickness of 5 μm or less is laminated to a conductive layer via an insulating layer; for providing a blind-hole composed of a hole perforating the copper foil layer and the insulating layer; and a bottom composed of the conductive layer in the laminate; for filling-up the blind-hole by a electro-plated copper in the time for depositing an electro-plated copper layer on a surface of the electroless-plated copper layer to make the total thickness of a copper layer provided on the insulating layer 15 μm or less, for providing of an etching resist layer having thickness of 15 μm or less and for etching of the copper layer.


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