The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

May. 02, 2012
Applicants:

Yimao Cai, Beijing, CN;

Jun Mao, Beijing, CN;

RU Huang, Beijing, CN;

Shenghu Tan, Beijing, CN;

Yinglong Huang, Beijing, CN;

Yue Pan, Beijing, CN;

Inventors:

Yimao Cai, Beijing, CN;

Jun Mao, Beijing, CN;

Ru Huang, Beijing, CN;

Shenghu Tan, Beijing, CN;

Yinglong Huang, Beijing, CN;

Yue Pan, Beijing, CN;

Assignee:

Peking University, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1253 (2013.01); H01L 45/04 (2013.01); H01L 45/122 (2013.01); H01L 45/1233 (2013.01); H01L 45/1273 (2013.01); H01L 45/146 (2013.01); H01L 45/1608 (2013.01); H01L 45/1616 (2013.01); H01L 45/1625 (2013.01);
Abstract

Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiOlayer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiOlayer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiOlayer over a substrate; fabricating a Al electrode layer over the SiOlayer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.


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