The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Jul. 25, 2012
Applicants:

Chang-yu Wu, Hsin-chu, TW;

Chih-chiang Chang, Hsin-chu, TW;

Shang-chih Hsieh, Yangmei, TW;

Wei-chih Hsieh, Taoyuan, TW;

Inventors:

Chang-Yu Wu, Hsin-chu, TW;

Chih-Chiang Chang, Hsin-chu, TW;

Shang-Chih Hsieh, Yangmei, TW;

Wei-Chih Hsieh, Taoyuan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4238 (2013.01); H01L 21/28123 (2013.01); H01L 29/78 (2013.01);
Abstract

Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.


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