The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Aug. 30, 2013
Hrl Laboratories, Llc., Malibu, CA (US);
Andrea Corrion, Oak Park, CA (US);
Keisuke Shinohara, Thousand Oaks, CA (US);
Miroslav Micovic, Thousand Oaks, CA (US);
Rongming Chu, Newbury Park, CA (US);
David F. Brown, Woodland Hills, CA (US);
Alexandros D. Margomenos, Pasadena, CA (US);
Shawn D. Burnham, Oxnard, CA (US);
HRL Laboratories, LLC, Malibu, CA (US);
Abstract
A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.