The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Jun. 19, 2014
Applicant:
Panasonic Corporation, Osaka, JP;
Inventor:
Kazuyuki Nakanishi, Osaka, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0607 (2013.01); H01L 27/0207 (2013.01); H01L 27/0921 (2013.01); H01L 27/118 (2013.01); H01L 27/11807 (2013.01);
Abstract
The present disclosure provides a layout of a semiconductor integrated circuit device that can assure a lot of substrate contact regions, and can surely suppress latch-up without increasing an area of a whole semiconductor integrated circuit and without significantly decreasing a decoupling capacitance element. In a margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on a P-type well. In the margin region, a transistor serving as a decoupling capacitance and a substrate contact are disposed as a pair on an N-type well.