The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Jul. 20, 2012
Applicants:

Tsang-yu Liu, Zhubei, TW;

Yi-ming Chang, Pingzhen, TW;

Tzu-min Chen, Zhongli, TW;

Inventors:

Tsang-Yu Liu, Zhubei, TW;

Yi-Ming Chang, Pingzhen, TW;

Tzu-Min Chen, Zhongli, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/16 (2006.01); H01L 21/56 (2006.01); H01L 27/146 (2006.01); H01L 23/31 (2006.01); H01L 23/58 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/561 (2013.01); H01L 23/16 (2013.01); H01L 24/94 (2013.01); H01L 27/14618 (2013.01); H01L 27/14683 (2013.01); H01L 23/3114 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/13022 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15788 (2013.01); H01L 2924/16235 (2013.01);
Abstract

An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.


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