The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Jun. 30, 2014
Prabhat Kumar, Fremont, CA (US);
Wei-sheng Lei, San Jose, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Prabhat Kumar, Fremont, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves applying an adhesive layer to a front side of the semiconductor wafer. A mask layer is laminated onto the front side of the semiconductor wafer, the mask layer covering and protecting the integrated circuits. The adhesive layer adheres the mask layer to the front side of the semiconductor wafer. The mask layer is patterned with a laser scribing process to provide gaps in the mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the mask layer to singulate the integrated circuits.