The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Sep. 27, 2012
Applicants:

Guokai MA, Shanghai, CN;

Yihua Jin, Shanghai, CN;

Daniel M. Lavery, Cupertino, CA (US);

Jianhui LI, Shanghai, CN;

Inventors:

Guokai Ma, Shanghai, CN;

Yihua Jin, Shanghai, CN;

Daniel M. Lavery, Cupertino, CA (US);

Jianhui Li, Shanghai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 8/52 (2013.01); G06F 9/30 (2013.01);
Abstract

A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.


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