The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Aug. 24, 2012
Jin-seong Heo, Suwon-si, KR;
Seong-jun Park, Seoul, KR;
Hyun-jong Chung, Hwaseong-si, KR;
Hyun-jae Song, Hwaseong-si, KR;
Hee-jun Yang, Seoul, KR;
David Seo, Yongin-si, KR;
Jin-seong Heo, Suwon-si, KR;
Seong-jun Park, Seoul, KR;
Hyun-jong Chung, Hwaseong-si, KR;
Hyun-jae Song, Hwaseong-si, KR;
Hee-jun Yang, Seoul, KR;
David Seo, Yongin-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.