The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Jan. 09, 2004
Applicants:

Mou-shiung Lin, Hsinchu, TW;

Jin-yuan Lee, Hsinchu, TW;

Ching-cheng Huang, Hsinchu, TW;

Inventors:

Mou-Shiung Lin, Hsinchu, TW;

Jin-Yuan Lee, Hsinchu, TW;

Ching-Cheng Huang, Hsinchu, TW;

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 24/97 (2013.01); H01L 23/36 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 23/642 (2013.01); H01L 23/645 (2013.01); H01L 2221/68363 (2013.01); H01L 2221/68377 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/20 (2013.01); H01L 2224/211 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/09701 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/351 (2013.01);
Abstract

An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.


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