The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Apr. 09, 2012
Applicants:

Chi-ta LU, Sanxing Township, Yilan County, TW;

Jia-guei Jou, New Taipei, TW;

Yi-hsien Chen, Changhua, TW;

Peng-ren Chen, Hsinchu, TW;

Dong-hsu Cheng, Tainan, TW;

Inventors:

Chi-Ta Lu, Sanxing Township, Yilan County, TW;

Jia-Guei Jou, New Taipei, TW;

Yi-Hsien Chen, Changhua, TW;

Peng-Ren Chen, Hsinchu, TW;

Dong-Hsu Cheng, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/00 (2012.01); H01J 37/317 (2006.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01); H01J 37/302 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01J 37/3174 (2013.01); G03F 1/36 (2013.01); G03F 1/70 (2013.01); H01J 37/3026 (2013.01); G03F 7/70441 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); H01J 2237/31764 (2013.01);
Abstract

The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.


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