The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2015
Filed:
Sep. 23, 2013
Dong-suk Shin, Yongin-si, KR;
Hyun-chul Kang, Seoul, KR;
Dong-hyun Roh, Suwon-si, KR;
Pan-kwi Park, Incheon, KR;
Geo-myung Shin, Seoul, KR;
Nae-in Lee, Seoul, KR;
Chul-woong Lee, Suwon-si, KR;
Hoi-sung Chung, Hwaseong-si, KR;
Young-tak Kim, Hwaseong-si, KR;
Dong-Suk Shin, Yongin-si, KR;
Hyun-Chul Kang, Seoul, KR;
Dong-Hyun Roh, Suwon-si, KR;
Pan-Kwi Park, Incheon, KR;
Geo-Myung Shin, Seoul, KR;
Nae-In Lee, Seoul, KR;
Chul-Woong Lee, Suwon-si, KR;
Hoi-Sung Chung, Hwaseong-si, KR;
Young-Tak Kim, Hwaseong-si, KR;
Abstract
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.