The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Jul. 28, 2011
Applicant:

Hui Zeng, Shenzhen, CN;

Inventor:

Hui Zeng, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/00 (2006.01); H05K 3/36 (2006.01); H05K 3/20 (2006.01); H05K 3/10 (2006.01); H05K 3/02 (2006.01); H05K 1/00 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4635 (2013.01); H05K 3/0097 (2013.01); H05K 2201/055 (2013.01); H05K 2201/0715 (2013.01); Y10T 29/49126 (2015.01);
Abstract

In a method for manufacturing multilayer PCBs having n circuit layers, a double-sided flexible substrate strip is provided. The strip comprises a number of PCB units, each comprising m segments, wherein m=n/2 if n represents an even integer, and m=(n+1)/2 if n represents an odd integer. Each segment includes two foil portions. In a reel to reel process, the strip is treated to form n−2 foil portions of each PCB unit into traces, further remove one foil portion if n represents an odd integer. The other two foil portions are left untreated. Then the strip is cut to separate the PCB units from each other. The PCB unit is folded in such a manner that the traces are arranged between the other two foil portions. The folded PCB unit is laminated to form a multilayer substrate and traces are formed in the two foil portions.


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