The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Jan. 13, 2014
Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

Sven Beyer, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Alexander Ebermann, Dresden, DE;

Carsten Grass, Dresden, DE;

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 21/283 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823835 (2013.01); H01L 21/02595 (2013.01); H01L 21/283 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/665 (2013.01);
Abstract

A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.


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