The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Jan. 13, 2014
Globalfoundries, Inc., Grand Cayman, KY;
Sven Beyer, Dresden, DE;
Alexander Ebermann, Dresden, DE;
Carsten Grass, Dresden, DE;
Jan Hoentschel, Dresden, DE;
GLOBALFOUNDRIES, INC., Grand Cayman, KY;
Abstract
A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.