The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Dec. 12, 2012
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Stephen Daley Arthur, Niskayuna, NY (US);

Kevin Sean Matocha, Starkville, MS (US);

Ramakrishna Rao, Niskayuna, NY (US);

Peter Losee, Starkville, MS (US);

Alexander Viktorovich Bolotnikov, Niskayuna, NY (US);

Assignee:

General Electric Company, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/42368 (2013.01); H01L 29/66068 (2013.01); H01L 29/66712 (2013.01); H01L 29/1608 (2013.01);
Abstract

An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.


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